1. Field of the Invention
An embodiment of the present invention relates to a semiconductor memory device. An embodiment of the invention to be disclosed includes a structure of a memory cell and a structure of an element included in the memory cell.
2. Description of the Related Art
As a memory cell in a semiconductor memory, one including two transistors (a reading transistor and a writing transistor), one capacitor, and one diode is known (for example, see Patent Document 1 and Patent Document 2). In this memory cell, a gate of the reading transistor is connected to the capacitor, and the writing transistor connected to a bit line for writing controls the charge and discharge of the capacitor. With this structure, storage and erasing of data is performed.
It is only necessary that the capacitor in the above memory cell has capacitance high enough to turn the reading transistor on; thus, the capacitor in the above memory cell has an advantage of having a smaller area than a dynamic random access memory (RAM) including one transistor and one capacitor.
However, in the memory cells each disclosed in Patent Document 1 and Patent document 2, electric charges stored in the capacitor are lost over time due to leakage current of the writing transistor even when the writing transistor is off, which is similar to the dynamic RAM. Therefore, in the case where a semiconductor memory device including the above memory cell operates, there is a problem in that data rewriting operation (refresh operation) needs to be performed frequently (every several tens of milliseconds) in order to hold the stored data.
In addition, the semiconductor memory device needs to have densely arranged memory cells in order to increase storage capacity. However, in the semiconductor memory including memory cells each of which includes a reading transistor, a writing transistor, and a capacitor as disclosed in Patent Document 1 and Patent Document 2, a word line and a bit line are provided to correspond to the reading transistor and the writing transistor, and thus, there is a problem of difficulty in high integration. Against the problems, a semiconductor memory device in which an area of a memory cell is reduced by employing a writing transistor with a vertical-channel structure provided over a source region of a reading transistor is disclosed (see Patent Document 3).